AR# 2729


CPLD - How do I control logic optimization in a CPLD?


General Description:

The CPLD fitter software will collapse all combinatorial logic in designs, either partially or completely.

However, it is possible to control the way in which the logic optimization is performed.


Collapsing Product Term Limit:

When a larger combinational logic function consisting of several levels of AND-OR logic is completely collapsed (flattened), the number of product terms required to implement the function may grow considerably. If the collapsing of a logic level results in a logic function consisting of more than the P-term limit (after Boolean reduction), the collapsing of that logic level is not performed and the function will be implemented using additional levels of AND-OR logic.

The fitter report (design_name.rpt) indicates the number of P-terms used for each logic function. You should see these numbers increase as you raise the P-term limit, until the design is fully flattened. At the same time, the internal combinational nodes will be eliminated until none remain.

Preventing the Collapse of a Logic Node:

Flattening typically increases the overall amount of P-term resources required to implement the design. Some designs that fit the target device initially may fail to fit if flattened too much. Other designs can be flattened completely and still fit. If you cannot increase the P-term parameter enough to sufficiently flatten a critical path and still fit the target device, you may apply the logic optimization control attribute "KEEP" to specific nodes in your design; the KEEP attribute prevents these nodes from being collapsed into their fan-outs.

If you have a "DATA" symbol in your schematic that you do not wish to be optimized out, place the KEEP attribute on DATA.

You may also apply this through a UCF file. The correct syntax is:


The KEEP attribute has no effect on any symbol that does not contain macrocell logic, such as an I/O buffer.

When the KEEP attribute is placed on a symbol, it inhibits logic optimization on all macrocells used to implement the symbol. For example, if you place KEEP on a macro symbol (e.g., Library Element - D2_4E), all outputs and internal nodes of the decoder will be prevented from collapsing. This is usually not desirable.

If you wish to prevent collapsing on a specific output signal from a macro symbol, place the KEEP attribute on the net itself. When you place the KEEP attribute on a net, the fitter applies the attribute only to the primitive symbol that drives that net.

If you have a net DOUT connected to your symbol DATA in your schematic that you do not wish to be optimized out, place the KEEP attribute on DOUT.

You may also apply this through a UCF file. The correct syntax is:


Forcing the Collapse of a Logic Node:

You can also force a logic symbol to collapse into all of its fanouts by placing the COLLAPSE attribute on the symbol or its output net.

The correct syntax to do this via a UCF file is:

NET NODE COLLAPSE; - on the output NET.

The COLLAPSE attribute affects all logic functions contained within a symbol. If you wish to force the collapsing of a multi-symbol logic chain, you may need to use multiple COLLAPSE attributes.

AR# 2729
日期 12/15/2012
状态 Active
Type 综合文章
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