AR# 2742


12.1 Timing Closure - How do I analyze the delays for a specific path?


How do I analyze the path delays between two pieces of logic in my design?


This capability is available only through the Timing Analyzer graphical software:

1. In ISE, expand the tree for Implement Design -> Place and Route -> and Generate Post-Place and Route Static Timing.
2. Double-click on "Analyze Post-Place and Route Static Timing (Timing Analyzer)".
3. Select Timing -> Run Timing Analysis and select "Analysis Type: Against User Specified Paths by Defining Endpoints...".
4. Select the sources and destinations on which you want to see the timing. Choose the Element Type (Flip-Flops, Pads, Nets, Pins, CLBs, Clocks). Use the filter to limit the choices (wild card characters are valid). Add the source elements to the Source area and add the destination elements to the Destination area.
5. Select the options and settings for this report, and click OK.
6. The timing report lists all of the paths from worst case (top) to best case (bottom).

NOTE: The "R" on the delays refers to Rising. The 'F" on the delays refers to Falling.

AR# 2742
日期 12/15/2012
状态 Active
Type 综合文章
器件 More Less
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