We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2756

Foundation XVHDL: How to keep internal signal name so it appears in simulator


Keywords: internal, signal, name, xvhdl, simulation

Urgency: Standard

General Description:
Some internal signals that are outputs of combinatorial logic
will not shows up as a selectable signal in the simulator due
to the XVHDL compiler changing the name of the signal.


To force Metamor (the XVHDL compiler) from renaming the signal
use the 'critical' attribute, as shown below.

Note that the Metamor library should be declared at the top of
the VHDL file:

library METAMOR;
use METAMOR.attributes.all;

The attribute should be used as follows, and should be placed
before the 'begin' keyword in the architecture section.

attribute critical of <signal name>: signal is true;
AR# 2756
日期 01/03/2000
状态 Archive
Type 综合文章