AR# 2776: Foundation F1.x XABEL: How to generate .PLD (Plusasm) file from XABEL
AR# 2776
Foundation F1.x XABEL: How to generate .PLD (Plusasm) file from XABEL
描述
Keywords: XABEL, PLD, Plusasm, abl2pld
Urgency: Standard
General Description:
By default, the XABEL synthesizer with Foundation F1.x writes out an EDIF (.EDN) file for the ABEL file. Is there a way to force XABEL to write out a PLD (Plusasm) file instead of an EDIF file?
解决方案
Assuming that the ABEL file is the top-level design file, it is possible to have XABEL write out a PLD file instead of an EDIF file. (If the ABEL file(s) are compiled as modules on a schematic, there is currently no way to force ABEL to write out PLD)
Sometimes it may be necessary to have XABEL write out a Plusasm (.PLD) instead of an EDIF (.EDN) file. Two possible reasons for doing this are:
*There are some XEPLD (Plusasm) Property statements which are only supported in Plusasm, and do not have Xilinx Property equivalents which are supported in EDIF. See (Xilinx Solution 3020) for details on supported Xilinx Properties. *There have been cases observed where using the EDIF flow provides less-optimal results in terms of device utilization. In these cases, it has been observed that using the Plusasm (PLD) flow instead of the EDIF flow can provide better device fitting results.
To enable the Plusasm flow, the SUSIE.INI must be editted. 1. From Foundation Project Manager, select File -> Configuration. 2. Hit the "View Ini File" button. 3. Find the line which says ;XABELNETLIST=PLUSASM. 4. Remove the ';' at the beginning of this line to "uncomment" it.
Now, when you synthesize the ABEL code, it should write out a .PLD file instead of .EDN, and this .PLD file will be read by the Xilinx M1 Design Manager.
Note that you may see an Error at the end of Synthesis, saying that Synthesis Failed. Assuming there are no "real" errors in the code, this error may be caused by the fact that Foundation expects to see an EDIF file (.EDN) at the end of the synthesis. Since only a .PLD file was generated, it thinks synthesis failed. You can check the log window in the Project Manager to see if this was the problem. If you see a line stating:
"abl2pld has succeeded..."
then you should be fine. Most likely, you'll also see some lines after this which state:
Hde: abl2edif.exe -failed Hde: <design>.EDN was not created
However, since abl2pld was successful, you should have a .PLD file, and be able to continue with the flow.
On a similar note, after abl2pld has completed, you may see that a dialog box appears indicating that abl2edif is running. You may hit the Cancel button on this, since we are only interested in the PLD file.
XABEL will synthesize the code to a PLD file, and the PLD file will automatically be read by the Design Manager when implementing the design. If the Design Manager has already been run previously in the project with the default EDIF flow, then the Design Manager project will need to be recreated. See (Xilinx Solution 3048) for more information on this topic.
To functionally simulate the design, follow these steps:
1. Enter the Design Manager from the Project Manager. 2. In Design Manager, select Design->New Version, then Design->New Revision. 3. Go into the Flow Engine (Tools->Flow Engine) 4. "Step" the flow, so that it goes only up through Translate. 5. Go back to Foundation Project Manager, and choose Tools->Checkpoint Simulation... 6. Choose the appropriate <device>.NGD file. 7. The Simulator will load the netlist for Functional Simulation.