UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 2831

Synplify - How do I force an IOB NODELAY latch or flip-flop in HDL (Verilog/VHDL)?

Description

General Description:

XC4000E/EX/XL IOB flip-flops and latches have a delay block between the external pin and the D input. The XC5200 IOB also provides a programmable delay element to control input set-up time. This delay prevents any possible hold-time violations if a clock signal is also coming into the device and clocking the input flip-flop or latch. You can remove this delay with the NODELAY attribute. The NODELAY attribute decreases the setup time requirements and introduces a small hold time.

Use the various options below to configure the NODELAY attribute for your particular system.

解决方案

For XC4000E/EX/XL, you can remove the default delay by instantiating a flip-flop or latch with a NODELAY attribute. Input flip-flops or latches with an _F suffix have a NODELAY attribute assigned to the cell. For example, the components IFD_F or ILD_1F remove this delay because these cells include a NODELAY attribute.

NOTE: Instantiating IFD_F in VHDL (v5.3.1 and earlier) results in IFD having an incorrect FAST attribute. (Synplicity is aware of this problem.) You can work around this issue by instantiating IFDX and passing the NODELAY attribute as follows:

attribute NODELAY: string;

attribute nodelay of <instance name> label is "TRUE";

However, the XC5200 IOB does not include flip-flops or latches; instead, it provides direct connections from each IOB to the registers in the adjacent CLB in order to emulate IOB registers.

You have the option of passing the "xc_nodelay" attribute through a constraints file (.sdc) or the HDL code.

# Vendor-specific constraints are passed in an .sdc file:

define_attribute {<input_port_name>} xc_nodelay 1

XC4000E/EX/XL only: Using Verilog code and instantiating an IFD_F

`include "/products/synplify/lib/xilinx/xc4000.v"

module ifd_ex (CLK, A, B, O);

input A ;

input B, CLK;

output O;

wire Q;

IFD_F U0 (.Q (Q), .D (A), .C (CLK));

// token logic

assign O = Q & B;

endmodule

XC4000E/EX/XL and XC5200: Using Verilog code and passing NODELAY through HDL

module ifd_ex (CLK, A, B, O);

input A /* synthesis xc_nodelay=1 */;

input B, CLK;

output O;

reg Q;

always @(posedge CLK)

Q <= A;

// token logic

assign O = Q & B;

endmodule

XC4000E/EX/XL and XC5200, using Verilog code and passing NODELAY through a constraints file (.sdc)

module ifd_ex (CLK, A, B, O);

input A;

input B, CLK;

output O;

reg Q;

always @ (posedge CLK)

begin

Q <= A;

end

// token logic

assign O = Q & B;

endmodule

# Vendor-specific constraints are passed in an .sdc file:

define_attribute A xc_nodelay 1

XC4000E/EX/XL only: Using VHDL code and instantiating an IFD_F

library IEEE;

use IEEE.std_logic_1164.all;

library xc4000;

use xc4000.components.all;

entity ifd_ex is

port (CLK, A, B : in STD_LOGIC;

O : out STD_LOGIC);

end ifd_ex;

architecture xilinx of ifd_ex is

signal Q : STD_LOGIC;

begin

U0 : IFD_F port map (Q => Q,

D => A,

C => CLK);

-- token logic

O <= Q and B;

end xilinx;

XC4000E/EX/XL and XC5200: Using VHDL code and passing NODELAY through HDL

library IEEE;

use IEEE.std_logic_1164.all;

entity ifd_ex is

port (CLK, A, B: in STD_LOGIC;

O: out STD_LOGIC);

attribute xc_nodelay : boolean;

attribute xc_nodelay of A : signal is true;

end ifd_ex;

architecture xilinx of ifd_ex is

signal Q : STD_LOGIC;

begin

U0: process (CLK)

begin

if (CLK'event and CLK='1') then

Q <= A;

end if;

end process;

-- token logic

O <= Q and B;

end xilinx;

XC4000E/EX/XL and XC5200: Using VHDL code and passing NODELAY through a constraints file (.sdc)

library IEEE;

use IEEE.std_logic_1164.all;

entity ifd_ex is

port (CLK, A, B: in STD_LOGIC;

O: out STD_LOGIC);

end ifd_ex;

architecture xilinx of ifd_ex is

signal Q : STD_LOGIC;

begin

U0: process (CLK)

begin

if (CLK'event and CLK='1') then

Q <= A;

end if;

end process;

-- token logic

O <= Q and B;

end xilinx;

# Vendor-specific constraints are passed in an .sdc file:

define_attribute A xc_nodelay 1

AR# 2831
创建日期 08/21/2007
Last Updated 12/15/2012
状态 Active
Type 综合文章