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The Divider Generator supercedes all previously released Xilinx Divider cores.
General LogiCORE IP Divider Generator Issues
(Xilinx Answer 22314) Why do I have extra or missing registers in my DSP48, DSP48E, or DSP48A A, B input path that cause my design to fail in timing simulation and hardware when using the MAP -timing option?
(Xilinx Answer 37326) Why do I receive a CARRYCASCIN DRC about a DSP48 Slice instance, in my simulation of Divider Generator core?
Maximum operand and output widths increased to 64 bits
Support for Virtex-7, and Virtex-7 Low Power with ISE 13.2
Support for Kintex-7, and Kintex-7 Low Power with ISE 13.2
Support for Artix-7 with ISE 13.2
Supported Devices (*)To access these devices in the ISE Design Suite, contact your Xilinx FAE.
Virtex-7 XT (7vx485t)
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XQ LXT/SXT
Virtex-6 -1L XC LXT/SXT
Spartan-6 XC LX/LXT
Spartan-6 XQ LX/LXT
Spartan-6 -1L XQ LX
Spartan-6 -1L XC LX
LogiCORE Divider Generator v3.0
Initial Release in the ISE 11.2 Design Suite
ISE 11.2 software support
Virtex-6 and Spartan-6 device support
CR517724 Fixed erroneous output for Divisor Width=48 for High Radix algorithm.
Incorrect output was given if the Divisor value was not maintained between valid inputs (i.e., when ND and RFD pins are high). Also note that for this Divisor width the maximum latency is now two cycles less than for version 2.0.
(Xilinx Answer 32553) Why are my simulation results incorrect, when targeting the High Radix implementation, with a divisor bit width of 48?
CR512188 Corrected bounds for Fractional Width in GUI for Radix-2 algorithm.
The bounds for Fractional Width in the GUI should have been 2 to 32 when Radix-2 algorithm was selected (as defined in the data sheet).
(Xilinx Answer 32552) Why do I receive an XST error when targeting the Radix-2 implementation, with a remainder fractional bit width of 0 or 1?
CR481526 Changed behavior of Radix-2 signed divider with fractional remainder so that magnitude of result is the same irrespective of sign. For example, the following is now true -(4/3) = -4/3.
The Radix-2 variant performs all divisions internally using positive quantities. The sign of the inputs and outputs is handled by complementers. However, an extra bit of internal precision retained on the input to the fractional output complementer meant that there could be a difference in the LSB between results that are positive or negative but of the same magnitude. The core has been modified to remove this extra bit, so that the magnitude of the result is the same irrespective of the sign of the inputs.
CR521010 Corrected throughput reported by GUI for High Radix divider with reduced latency.
The GUI reports maximum sustained throughput for the High Radix divider. The GUI for version 2.0 did not account for latency less than the maximum value. As such, it might be incorrect when a latency less than the maximum value is set manually. The GUI now correctly reports throughput for latency values less than the maximum.
Software Support for the Virtex-6 Lower Power parts was added in this release, but this IP is not yet supported and cannot be generated from CORE Generator. In order to work around this issue, you can set your project to target an equivalent Virtex-6 LXT device which will allow you to generate a place holder IP that can be regenerated when support for the Virtex-6 Lower Power parts is added in 11.3.
LogiCORE IP Divider Generator v2.0 Initial Release in ISE 10.1 IP Update 2
Support for Virtex-5 and Spartan-3A DSP devices
Introduction of High Radix implementation to replace Division by Repeated Multiplications