UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29170

11.3 System Generator for DSP - Why do I see simulation mismatches at the beginning of my HDL simulation generated from System Generator for DSP if Synplify is used for synthesis?

描述

Why do I see simulation mismatches at the beginning of my HDL simulation generated from System Generator for DSP if Synplify is used for synthesis?

解决方案

This can be caused by a known issue in which Synplify and Synplify Pro incorrectly optimize constants that drive shift register delay lines such that the delay is removed and the constant value is presented earlier than intended.

AR# 29170
日期 05/22/2014
状态 Archive
Type 综合文章
的页面