UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29290

14.x Timing Analyzer - "WARNING:Timing:3223 - Timing constraint "%s" ignored during timing analysis."

描述


The following warnings appear in the static timing report:
"WARNING:Timing:3223 - Timing constraint "%s" ignored during timing analysis."
"WARNING:Timing:3225 - Timing constraint %s ignored during timing analysis"

解决方案


The constraint will be ignored if other constraints with higher priority override it or there is no element in the timegroup. The warning can also be caused by there being no synchronous data paths between the elements in the referenced timing group.
Suggestions:
A. Run a TSI (Time Spec Interaction) report to determine which constraints interacted with the constraint in question.

B. Confirm that the elements of the Time Groups are synchronous elements in FPGA Editor. Use the Query TimeGrps command from Timing Analyzer to produce a report of the elements of the Time Groups.
AR# 29290
日期 02/07/2013
状态 Active
Type 综合文章
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • ISE Design Suite - 14.2
  • ISE Design Suite - 14.3
  • ISE Design Suite - 14.4
  • Less
的页面