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AR# 2951

XABEL/Foundation F1.3/Alliance: Using F1.3's XABEL with Alliance packages (mentor, viewlogic)

Description

Keywords: abel, alliance, viewlogic, workview office, mentor,
ds371

Urgency: Standard

General Description:

Starting with the M1.3/F1.3 software release, the XABEL product
will only be available as part of the Foundation Series
software tools. A stand-alone XABEL product (previously DS371)
will no longer be available. Existing in-warranty DS371
customers who use Xilinx Alliance series software will
automatically receive a Foundation Series F1.3 software
package with which to compile their ABEL code. Below are the
instructions on how to install and use ABEL with F1.3 and
Alliance packages. (This information was included with the
shipment of this upgrade)

解决方案

XABEL Flow Using Foundation

This document will provide instructions for installing the
appropriate software, compiling Abel files in Foundation, and
then incorporating the resultant netlist into a 3rd party
schematic design.

Install the M1.3 Alliance Implementation Tools
1.) Install the Alliance Series vM1.3 Core Technology CD as
instructed in the Alliance Series vM1.3 Release Notes.

Install the Foundation Design Entry Tools
The amount of disk space available and the extent to which
you wish to use the Foundation tools will determine how much
software is installed from this CD.
2.) Insert the Foundation F1.3 Design Entry Tools CD.
3.) When the Master Install screen appears, choose "Design
Entry Tools." If the Master Install Screen does not automatically pop up, run the Setup.exe program from the CD.
4.) Follow the instructions on the screen. When asked which
type of setup to run, choose Custom.
5.) On the Select Components screen, you will have the option
to install various portions of the software. To reduce the
amount of disk space required, you may select to not install
the sample projects, or just install those which involve
Abel. You may also choose to only install those libraries
for the devices you will be targetting. Below is a summary
of the available components:

Program Files - Required
X-VHDL - Not Required. Requires separate license to run.
Sample Projects - Not required, but you may want to install
just the Abel projects
System Libraries - At least one required. You may choose
only those families you will be targetting.
Keylock Drivers - Not required. (Only required for X-VHDL)

Even with a minimal install, you will have the ability to use
all features of the Foundation software, with the exception
of the X-VHDL compiler.

6.) Complete the Foundation Design Entry Tools installation
as instructed.

Install the Foundation Design Implementation Tools
7.) Return to the Master Install screen, and select "Design
Implementation Tools"
8.) When prompted, install the Foundation Design
Implementation Tools CD.
9.) Run Setup.exe, if the Install Shield does not
automatically start.
10.) Follow the instructions on the screen. The installation
directory should be the same directory that the Alliance
Core Tools were installed to. (By default, C:\Xilinx)
11.) When asked to select type of installation:
11a.) If you plan to use the Foundation tools for Abel
compilation only, choose "Design Entry Tool Components
Only."
11b.) If you plan to use the Foundation tools for schematic
entry or simulation as well as Abel compilation, choose
"Typical Installation." When asked to select product
type, choose Base or Standard. When asked to select
"Software Components to Install" choose only Core
Executables and Xabel Interface. This assumes
that the full Implementation Core Tools have already
been installed from the Alliance CD, as in step 1.).
12.) Complete installation as instructed.

Using Foundation to Compile Abel Macros
The following procedure outlines the basic flow for creating
a project in Foundation and compiling one or more Abel
macros for incorporation into a 3rd party schematic. For
complete documentation of the Foundation Design Entry tools
and the XABEL interface, refer to the Online Help in the
Foundation Project Manager (Help->Foundation Help Contents).

1.) Invoke the Foundation Project Manager.
2.) Create a new project by selecting File -> New Project.
3.) Choose the appropriate design directory and family.
4.) Invoke the HDL Editor by clicking on the HDL Editor
button in the Project Manager.
5.) Select "Existing File", and browse to find the .ABL file.
6.) Since the Abel file will be a module in a top-level
schematic, be sure that the "Macro" compile switch is
selected in the Synthesis->Options dialog.
7.) To synthesize the Abel code, select Synthesis ->
Synthesize.
8.) A .EDN netlist file will be created for the module and
placed in the project directory.
9.) Follow the instructions below for incorporating this .EDN
netlist into a Viewlogic Workview Office or Mentor
Graphics schematic design.


Viewlogic Workview Office
=========================

Once you have created the EDIF file in the Foundation
environment, you must instantiate that EDIF in your Viewlogic
schematic.

Create a new symbol for the ABEL module complete with input
and output pins. Make sure that all the input and output
ports match the symbol by name. Use square brackets for bus
notation: BUS[3:0]. If a symbol created by SYMGEN already
exists, simply remove the DEF=XABEL and FILE=abelfile.ABL
properties before continuing.

Two more properties must be added to complete the symbol.
Right-click in the symbol window (but outside the symbol box
itself) and select Properties. Under the Block tab, change
the Symbol Type to Module. This will prevent the EDIF
netlister from looking for an underlying schematic. Then,
under the Attributes tab, add an attribute with a Name of
FILE and a Value of abelfile.EDN. If the EDIF file is not
located in the project directory, then the full path to the
.EDN file must be specified.

If the ABEL code is modified in such a way that the input or
output ports are modified, then the symbol will have to be
manually updated to match the new ABEL module.

Because the ABEL module does not have a gate-level
representation within the Viewlogic realm, the design will
have to be compiled through NGDBUILD in order to process the
ABEL portions before performing a functional simulation.
Chapter 4 of the Viewlogic Interface and Tutorial Guide describes this process.
There is also a pushbutton solution
available for these steps. Solution #1985 in the Xilinx
Solutions Database contains the files and setup instructions
for this flow.

No changes to the timing simulation flow are required.

This procedure applies to Powerview users as well, although
some of the commands listed above will differ slightly for the workstation version of ViewDraw.


Mentor Graphics Design Architect
================================

Once you have created the EDIF file in the Foundation
environment, you must instantiate that EDIF in your Mentor
Graphics schematic. Note that, since this EDIF file comes from
a Windows 95/NT environment, you should run a DOS-to-UNIX
file-conversion utility (such as dos2unix) on this EDIF file
to avoid possible file-format problems.

Create a new symbol for the ABEL module complete with input and
output pins. Make sure that all the input and output ports
match the symbol by name. Use parentheses for bus
notation: BUS(3:0). If a symbol created by SYMGEN already
exists, simply remove the DEF=XABEL and FILE=abelfile.abl
properties before continuing.

One more property must be added to complete the symbol. With
the symbol for the ABEL module loaded into the symbol editor,
select Right Mouse Button ? Properties (logical) ? Add
Single Property. For Property Name, enter FILE. For Property
Value, enter abelfile.edif, where abelfile is the name of the
ABEL module represented by this symbol. If the EDIF file is
not located in the project directory, then the full path to the
.edif file must be specified.

If the ABEL code is modified in such a way that the input or
output ports are modified, then the symbol will have to be
manually updated to match the new ABEL module.

Because the ABEL module does not have a gate-level
representation within the Mentor realm, the design
will have to be compiled through NGDBUILD and PLD_EDIF2SIM in
order to process the ABEL modules and generate a suitable
simulation model for PLD_QuickSim. PLD_QuickSim must then be
run on the output netlist from PLD_EDIF2SIM. (To annotate
simulation values to the original schematic, you may enable
cross-probing in PLD_QuickSim). Chapter 6, <93>Mixed Designs
with Schematic on Top<94> in the Mentor Graphics Interface/Tutorial Guide, describes this process in the
<93>Functional Simulation After Synthesis<94> section.

No changes to the timing simulation flow are required.

AR# 2951
创建日期 08/31/2007
Last Updated 10/06/2008
状态 Archive
Type 综合文章