AR# 2962


Foundation F1.3/F1.4 XVHDL: Using Input/Output latches


Keywords: latch, ild, inlat, iob, merge, metamor

Urgency: Standard

General Description:

How can I implement I/O Latches through the Foundation
XVHDL compiler?



For XC3000/A and XC4000/E devices, an I/O Latch primitive
such as an ILD, must be instantiated in the VHDL code. The
following is an example of such code:

library IEEE;
use IEEE.std_logic_1164.all;

entity in_lat is
port (
d_in: in STD_LOGIC;
g_in: in STD_LOGIC;
q_out: out STD_LOGIC

attribute inhibit_buf: boolean;
attribute inhibit_buf of d_in: signal is true;
--this attribute is necesssary to prevent the
--compiler from inserting an IBUF at the port,
--since the IBUF is included in the ILD component.
end in_lat;

architecture in_lat_arch of in_lat is

component ILD -- component declaration
port (D: in STD_LOGIC;
Q: out STD_LOGIC);
end component;


U1: ILD port map (d_in, g_in, q_out); --instantiation

end in_lat_arch;


For XC4000EX/XL devices, the i/o latch may be instantiated as
described in resolution #1, OR, the latch may be behaviorally
described in the VHDL code. If the latch is behaviorally
described, the XVHDL compiler will infer a regular CLB latch,
but the MAP phase of the implementation flow has the capability
to then merge the latch into the IOB. If this method of
implementation is desired, one of the following MAP options
must be used when implementing the design with the Xilinx
Design Manager:

MAP -pr i <indicates merging into "input" latches>
MAP -pr o <indicates merging into "output" latches>
MAP -pr b <indicates merging into "input" or "output latches>

To tell MAP to run with this command-line switch, use the
Template Manager to "customize" the Implementation Template.
For detailed instructions on how to do this, refer to
(Xilinx Solution 1227).

Below is an example of VHDL code which would infer a latch
which could then be merged into an IOB by MAP:

--The IEEE standard 1164 package, daclares std_logic, rising_edge(), etc.
library IEEE;
use IEEE.std_logic_1164.all;

entity d_latch is
port (GATE, DATA: in std_logic; Q: out std_logic);
end d_latch;

architecture BEHAV of d_latch is


process (GATE, DATA)
if (GATE ='1') then
Q <= DATA;
end if;
end process;
end BEHAV;
AR# 2962
日期 01/02/2000
状态 Archive
Type 综合文章
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