1. DCI CASCADE is only supported in Virtex-5 (and newer families Virtex-6 and 7 series) devices.
2. DCI CASCADE is enabled by putting the following constraint in the design constraint file (.ucf file).
a. Config DCI_CASCADE = "master_bank_number slave1_bank number slave2_bank_number ";
3. DCI banks cascaded together must be in the same column.
4. DCI compatibility rules apply across all DCI CASCADED banks.
a. Same VCCO on all cascaded banks if applicable.
b. Same VREF on all cascaded banks if applicable.
c. No more than one I/O standard using Split Termination across cascaded banks.
d. No more than one I/O standard using Single Termination across cascaded banks.
e. Please refer to Chapter 6 of the user guide for a completed understanding of all DCI related compatibility banking rules.
5. DCI banks cascaded together must be consecutive (no bank skipping is allowed). This only applies to Virtex-5; pass through banks are allowed in Virtex-6 and 7 series FPGAs.
6. Banks 1and2 can only be used as slave banks since there are no VRPand VRN pins available for these two banks.
7. DCI CASCADE cannot across bank 0 which is located in between band 1and2 in the center column.
8. DCI CASCADE cannot across Clock Management Tiles (CMT) which are located in between bank 3and 4, and bank 4and 6 in the center column for some Virtex-5 devices
(NOTE:ISE 9.2i or older version toolsmight miss this hardware limitation).
9. There must be at least one DCI I/O (even a dummy one) instantiated in the master bank, and this DCI I/O must require the use of VRP and VRN reference resistors for DCI termination referencing.
10. NOTE: For a complete understanding on all DCI and DCI CASCADE related rules, please consult Chapter 6 of the latest Virtex-5 User Guide and the latest Software Constraints Guide.
11. When runningbitgen via a command line or script, it is required to include the ".pcf" file. The ".pcf" file is read into bitgen to include DCI_CASCADE attributes. This is the default attribute for bitgen, but the ".pcf" must be present.