AR# 2989


Foundation F1.3, XVHDL 3.0.2: Error L20/CO: The Xilinx 4ke library does not contain a latch (#480 Constraint)


Keywords: latch, 4ke, RAM, Metamor, L20/C0, #480 Constraint

Urgency: Hot

General Description:

When synthesizing a VHDL design in Foundation F1.3, the
following error may result:
"Error L20/C0: #480 Constraint: The Xilinx 4ke library does not
contain a latch."


The XC3000 and XC4000E architectures do not contain latches
in the CLBs. In the XC3000 devices, latches are implemented
with combinatorial gates which cause combinatorial feedback
loops, and therefore is not advised. In the XC4000E family,
there is another option for implementing latches, which is to
use the on-chip CLB RAM, which will provide the same
functionality as the latch, but without the combinatorial
feedback loops.

In Foundation 6.0.2, the XVHDL compiler would actually infer
RAM when latches were described in an XC4000/E VHDL design.
In F1.3, this functionality of the XVHDL compiler disappeared,
and instead, an error was issued saying that the 4ke library
does not contain latches. This left many designs which once
compiled fine in Foundation 6.0.2 (by inferring RAM), to not
compile at all in Foundation F1.3.

A patched version of the XVHDL compiler (v3.0.3) is now
available which brings back the old functionality of inferring
RAM for 4KE latches. This new version is available in the
File Download area of the Xilinx Answers area on the Xilinx
Web site.

**Note: This fix is included in Foundation F1.4
AR# 2989
日期 01/02/2000
状态 Archive
Type 综合文章
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