This answer record contains the Release Notes and Known Issues list for the CORE Generator tool and LogiCORE IP YCrCb to RGB Color-Space Converter Core.
The following information is listed for each version of the core:
LogiCORE IP YCrCb to RGB Color-Space Converter (YCrCb2RGB) core IP Page:
https://www.xilinx.com/products/intellectual-property/ycrcb_to_rgb.html
General LogiCORE IP YCrCb to RGB Color-Space Converter Issues
(Xilinx Answer 33386) | 11.3 CORE Generator - Licenses for certain free cores are now part of the software install |
LogiCORE IP YCrCb to RGB Color-Space Converter v6.01.a
Resolved Issues (ISE)
(Xilinx Answer 51589) | Why does the Video IP stop working (i.e., producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
(Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
(Xilinx Answer 52212) | Software Driver v5.00.a - Why do the drivers fail to compile? |
Resolved Issues (Vivado)
(Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
(Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
Known Issues (ISE)
(Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
Known Issues (Vivado)
(Xilinx Answer 52215) | Why does my core fail timing with an Critical Warning? |
LogiCORE IP YCrCb to RGB Color-Space Converter v6.00.a
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues (ISE)
(Xilinx Answer 51589) | Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK? |
(Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
(Xilinx Answer 52212) | Software Driver v5.00.a - Why do the drivers fail to compile? |
Known Issues (Vivado)
(Xilinx Answer 50909) | 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow? |
(Xilinx Answer 51483) | Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core? |
LogiCORE IP YCrCb to RGB Color-Space Converter v5.00.a
Initial release in ISE 14.1 and Vivado 2012.1 tools |
Supported Devices (ISE)
Supported Devices (Vivado)
New Features
Bug Fixes
Known Issues
LogiCORE IP YCrCb to RGB Color-Space Converter v4.0
Supported Devices
New Features
Bug Fixes
Known Issues
LogiCORE IP YCrCb to RGB Color-Space Converter v3.0
New Features
Bug Fixes
Known Issues
LogiCORE IP YCrCb to RGB Color-Space Converter v2.0
New Features
Bug Fixes
Known Issues
(Xilinx Answer 37987) | Where can I find UG762: Xilinx Streaming Video Interface User Guide? |
LogiCORE IP YCrCb to RGB Color-Space Converter v1.0
New Features
Bug Fixes
Known Issues
AR# 29980 | |
---|---|
日期 | 07/16/2018 |
状态 | Archive |
Type | 版本说明 |
IP |