AR# 3031


** OBSOLETE** V1.5, V1.4 COREGEN, WORKVIEW OFFICE, M1: Implemented module has much higher CLB counts than specified in the datasheet


Keywords: DSP, CLB, specs, rlocs, workview, viewlogic

Urgency: Standard

General Description:
When Coregen generates certain DSP modules, the result
sometimes utilizes many more CLBs than specified in the
datasheet for the specific Core.

This problem has been observed when Coregen is set to
generate a symbol in Workview Office. The increase in CLB
utilization is associated with the loss of RLOC properties
generated by Coregen when the Viewlogic database is
generated for the module.


If you are using Workview Office:

In Viewdraw, open up the symbol generated by Coregen in
the Viewdraw symbol editor. Double click on the symbol for
the Coregen block and click on the attribute tabs.
The LEVEL attribute must be set to "XILINX".

If LEVEL=VHDL or something else, change it to LEVEL=XILINX.

Write out a new EDIF file and re-implement the design. The
implementation of the new EDIF file should require much
fewer CLBs than the previous one.
AR# 3031
日期 09/26/2000
状态 Archive
Type 综合文章
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