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AR# 30509

9.2.01 - System Generator for DSP - Why do I get hold timing violations attributed to large clock skew when I target my custom Spartan-3A DSP JTAG Hardware Cosimulation target?


When I try to generate my design to a hardware cosim block, I get timing errors in PAR as a result of hold violations and do not get a hardware cosim block.


Some minor changes to the hardware cosimulation logic for Spartan-3A DSP parts cause hold time violations to be common for this device when targeting a JTAG hardware cosimulation target.

There is a large clock skew in these designs because the tools must take into account the worst case of both clocks driving the BUFGMUX.

To work around this issue, add two TIG (Timing IGnore) constraints to the board UCF file to ignore the "single step" clock into both BUFGMUX's. Since this clock is driven by BSCAN logic being driven by Simulink, the timing is not critical and can be ignored.

1. Locate the UCF for the target board (i.e. <System Generator install directory>\sysgen\plugins\compilation\Hardware Co-Simulation\my_board\my_board.ucf).

2. Add the following lines to the end of the constraint file:



3. Save the changes to this file and regenerate your hardware cosimulation block.

AR# 30509
日期 12/15/2012
状态 Active
Type 综合文章