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AR# 3051

CPLD - Translating Lattice LDF file to Xilinx XABEL format

Description

Keywords: ABEL, translation

Following are some hints that should help you translate a Lattice LDF file format to Xilinx ABEL.

解决方案

Technology Conversion: Helpful hints on translating Lattice LDF files to Xilinx ABEL format

This Answer Record assumes that you have some basic knowledge of the ABEL language.

The first step required is to delete all the extra lines that will not be needed in the LDF to XABEL conversion. These are the first lines of code in the LDF file that makes conversion cleaner when deleted.

Delete the lines that look like the following:
"LDF 1.00.00 DESIGNLDF;"
"DESIGN CONT 1.00;"

Delete the line that starts with: "PROJECTNAME"
Delete the "DECLARE" line
Delete the "END" line

Then, proceed to delete every line that starts with "SYM", and every "END" line. Also, make sure you leave a blank line in the places where you deleted these lines to preserve some easy to see modularity during conversion.

Every GLB module in the LDFfile has a signal declaration describing which will be the outputs that the GLB module will generate. Some of these signals map to the physical ports and some of them are used as internal nodes that can span among other GLB modules.
------------------------------------------------------------------------------

The following are generic cases that are seen in a typical LDF file, along with their equivalent XABEL translation.

Following are two examples of output signal declarations within a GLB module.

Signal declaration of non-registered signal in LDFfile

SIGTYPE IRAM0 ASYNC OUT;

In the ABEL code, add the following to the signal declaration list if signal is a pin:
IRAM0 pin istype 'reg';

In the ABEL code, add the following to the signal declaration list if signal is just an internal signal:
IRAM0 node istype 'reg';

------------------------------

Signal declaration in ldf file of a JK flip flop

SIGTYPE ICAS3 REG OUT;
FJK11 (RCNTR ,JROW_COL,KROW_COL,ICLK);

In the ABEL code, add the following to the signal declaration list if signal is internal:

ICAS3 node istype 'reg_jk';

In the ABEL code, add the following to the signal declaration list if signal maps to a physical pin:

ICAS3 pin istype 'reg_jk';

In the ABEL code, add the following to the EQUATIONS declaration:

ICAS3.J = JCAS3;
ICAS3.K = KCAS3;
ICAS3.CLK = ICLK;

Where "JCAS3" is a signal that maps to the J input, "KCAS3" maps to the K input, and "ICLK" maps to the CLK input.

----------------------------

Signal declaration in ldf file of a flip flop

SIGTYPE XCRTS REG OUT;
XCRTS.CLK = IICLK;

Where "IICLK" is the clock signal that connects to the flip flop.


In the ABEL code, add the following to the port declaration if the flip flip is only used internally:

XCRTS node istype 'reg';

In the ABEL code, add the following to the port declaration if the flip flop is also used as a physical pin:

XCRTS pin istype 'reg';

Add the following to the EQUATIONS declaration:

XCRTS.CLK = IICLK;

where IICLK is the system clock signal.

Note that only one registered output in the GLB declaration has to have a clock assignment. The others do not have to be explicitly connected to the clock since in the architecture when one registered output is connected to the clock in one GLB the other registers have no other choice than to connect to the same clock signal. So if you find a "SYGTYPE XXXX REG OUT" declaration in a GLB module, look for the clock that drives any of the output registers in the GLB module if you cannot find the clock assignment for "XXXX."

--------------------------------

How do I know whether a signal is a node or an output pin?
Answer:
If the signal is a pin you will see the same signal name included in a line next to a text line that starts with "XPIN" meaning this signal is connected to a physical pin.

How do I know whether a registered signal is a JK flip flop or a D flip flop?
Answer:
If the registered signal is a JK flip flop you will see this signal included in a line that starts with the text pattern "FJK11" like the following:

FJK11 (RCNTR ,JROW_COL,KROW_COL,ICLK);

Where RCNTR is the signal coming from this register.

On the other hand, if the signal comes from a D flip flop you will see this
signal present in a line that looks like the following:

RQ0.CLK = ICLK;

Where "ICLK" is the signal that drives the clock of the D flip flop. Keep in mind a JK flip flop implementation will "cost" you two registers when using the Lattice architecture.

---------------------------------------------------------------------------

Keep in mind there are signals inside the GLB that are not declared anywhere in the code. These signals are local within the GLB and have to be declared in the ABEL code as "node."

-----------------------------------------------------------------------------

This is an example of a non registered output pin that takes the signal IRAM0 to the outside world. The signal "XIRAM0" would be used only if a pin feedback is required. Note that IRAM0 has to be declared as "SIGTYPE" before it can be connected to a physical output pin.

SYM IOC IO46 1 ;
XPIN IO IRAM0;
OB11 (XIRAM0, IRAM0);
END;

In the ABEL code add the following to the signal declaration list:
IRAM0 pin;
-----------------------------------------------------------------------------
This is an example of how the input clock signal is declared in the ldf file. The word "CLK" tells the software to use global resources for this signal:

SYM IOC Y0 1 ;
XPIN CLK XSYS_CLK LOCK 20;
IB11 (ICLK,XSYS_CLK);
END;

In our software we do not need to tell the synthesizer that a signal will use a global resource so the following will be the equivalent translation in ABEL:

ICLK pin;
-----------------------------------------------------------------------------

This is an example of a registered input pin. The signal "IA13" is the signal that will be used in the code. "IICLK" is the clock that this registered pin uses:

SYM IOC IO17 1 ;
XPIN IO XA13;
ID11 (A13,XA13,IICLK);
END;

In the ABEL code add the following to the signal declaration:

A13 pin istype 'reg';

In the ABEL code add the following to the EQUATIONS declaration:

A13.clk = IICLK;)

------------------------------------------------------------------------------


Converting equations

Equations are pretty much identical between XABEL and LDF format. However, the only difference that was found is that the "$$" in the LDF file actually is a "$" in ABEL, which means XOR.

------------------------------------------------------------------------------

Hints when translating macros

Macros generally have the following format in the LDF file:

LDFMACRO(OUTPUT1, OUTPUT2, INPUT1, INPUT2);

Note that the outputs are located in the left side while the inputs of the macro are on the left side.

If you would like to help make this Answer Record more complete and useful, send an email to:
hotline@xilinx.com
AR# 3051
创建日期 08/21/2007
Last Updated 07/28/2009
状态 Archive
Type 综合文章