We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 310

FITNET DRC error, flip flop using both SET and RESET


While processing a schematic design, the following error may be issued:

FITNET reports the following error during design fitting:

cl446:[Error]FFB output <signal> has been declared with both a .RSTF and
a .SETF equation. Only one is allowed or redeclare for high-density FB.



This error may be issued if the signal reported has been placed in a Fast
Function Block (due to pin assignment, or if the design targets an XC7318 or
XC7336). It is not legal to use both the PRE and CLR inputs to flip-flops that
are placed in a Fast Function Block.

Check the schematic and repartition the flip-flop into a High Density Function
Block if possible. If the design targets an XC7318 or XC7336, the logic may
need to be redesigned to use synchronous SET and RESET inputs.


This error can be issued even if the schematic appears correct.

The most common situation is that a flip-flop symbol with both PRE and CLR
pins (such as an FDCP) is placed on the schematic, and either one or both pins
are tied to GND.

The fitter may still interpret the PRE and CLR pins as being used in the design.

Replace the flip-flop with a library component that has only the necessary
AR# 310
日期 10/01/2008
状态 Archive
Type 综合文章