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AR# 31183

System Generator for DSP 10.1 - Why don't I see accurate cycle latency between a From Register and a To Register block in a Multiple sub-system / multiple clock System Generator simulation?


When I simulate a design in Simulink, if it includes From Register/To Register blocks, I do not see an accurate latency for signals crossing between the clock domains.


When simulated across different time domains, the shared memory blocks in System Generator are not cycled accurately. This is because the nature of Simulink does not allow true asynchronous simulations between the two domains.  


In any case, since the intent is to model asynchronous domains, you should not rely on the exact timing of passing signals between domains. It is important that "valid data" flags be used when crossing clock domains. 


To see a more accurate timing picture, you should generate the design and do behavioral/timing simulation in ISE.

AR# 31183
日期 05/22/2014
状态 Archive
Type 综合文章