When I run a design, there are errors in the PAR report similar to those below, however, the Project Navigator GUI does not show that an error occurred, nor is an error reported in the console:
__ERROR__
ERROR:Route:472 -
This design is unrouteable.
To evaluate the problem please use fpga_editor.
Routing Conflict 1:
Net:sys_clk_bufg on pin OCLK on location ILOGIC_X2Y145
Net:clk_bufio<0> on pin CLK on location OLOGIC_X2Y145
Conflict detected on wire: My_in(60611,106792)
Routing Conflict 2:
Net:sys_clk_bufg on pin OCLK on location ILOGIC_X2Y147
Net:clk_bufio<0> on pin CLK on location OLOGIC_X2Y147
Conflict detected on wire: My_in(60611,109992)
Routing Conflict 3:
Net:sys_clk_bufg on pin OCLK on location ILOGIC_X2Y153
Net:clk_bufio<0> on pin CLK on location OLOGIC_X2Y153
Conflict detected on wire: My_in(60611,119592)
Routing Conflict 4:
Net:sys_clk_bufg on pin OCLK on location ILOGIC_X2Y154
Net:clk_bufio<0> on pin CLK on location OLOGIC_X2Y154
Conflict detected on wire: My_in(60611,122784)
This issue is caused by Project Navigator overwriting the PAR return code for an unroutable design. The overwrite is a temporary solution to allow FPGA Editor to open a design that failed routing.
This problem has been fixed in the latest 10.1 Service Pack available at:
http://www.xilinx.com/support/download/index.htm
The first service pack containing the fix is 10.1 Service Pack 2
AR# 31213 | |
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日期 | 05/13/2010 |
状态 | Archive |
Type | 综合文章 |