AR# 3123


CPLD XC9500/XL/XV CoolRunner-II/XPLA3 - How are the initial states of flip-flops determined on Xilinx CPLDs?


I want the power-up state of a flip-flop to be a logic High ("1"). What type of flip-flop should I use to achieve this? Is there a property that I can attach to a flip-flop so it powers up into a "1" state?


When the default software settings are used, flip-flops are initialized with a "0." However, when you add the attribute "INIT=S," any flip-flop with this attribute powers up in the "1" state.

For example, with a flip-flop instance named "TEST," add the following to your UCF:


A global setting in the software enables you to set all registers to initialize to a "1," "0," or "FPGA Equivalent." The first two settings are self-explanatory. "FPGA Equivalent" means that if there is a register in your design that is using a Preload signal but no Clear signal, this register will initialize itself with a "1" on power up. This setting is called "Default Power-up Value of Registers" and is located under the Basic tab in the "Implement Design" preferences.

In your ABEL code, you can add the following:

xilinx property 'init=s reg_name' ;

Also, add one of the following (depending on whether the register is a node or drives an output pin):

reg_name PIN istype 'reg_name default_1'; // or default_0

reg_name NODE istype 'reg_name default_1'; // or default_0

NOTE: The second line is necessary to ensure proper register initialization for functional simulation.

You can verify the register initial states by looking at the fitter report (design.rpt):

ISE Version 8.x,7.x

In the HTML report, look for the section labeled Logic. There is a column for Reg Init State. Cross-reference the row (register name) with this column to identify the power-up state for that register.

ISE Version 6.x, 5.x

Look for the section labeled: "Resources Used by Successfully Mapped Logic." There is a column for "Reg Init State." Cross-reference this column with the signal name (row) to identify the power-up state of each register.

ISE Version 4.x

- All registered equations have a .PRLD (abbreviation for "Preload") extension.

- If the .PRLD extension equals GND, the register initializes to "0."

- If the .PRLD extension equals VCC, the register initializes to "1."

For other common CPLD questions, see the CPLD FAQ at: (Xilinx Answer 24167).

AR# 3123
日期 12/15/2012
状态 Active
Type 综合文章
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