We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 31275

LogiCORE Viterbi Decoder v6.2 - How is the latency for the core determined?


How is the latency for the core determined?


The latency of the core depends primarily on the traceback and constraint lengths. The latency is given by the number of symbol inputs between DATA_IN, validated by CE, or ND in the serial case, and the decoded data result output on DATA_OUT validated by RDY.

The general equation is as follows:

Latency = n*traceback_length+constraint_length where n = 2 for reduced latency and 4 for all other cases

The total latency figure is dependent on other factors like Best State, Speed Optimization, etc., in order to get the total latency the decoder should be simulated.

AR# 31275
日期 12/15/2012
状态 Active
Type 综合文章