AR# 31572: Endpoint Block Plus Wrapper v1.9, v1.9.1, v1.9.2, v1.9.3, and v1.9.4 for PCI Express - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)
Endpoint Block Plus Wrapper v1.9, v1.9.1, v1.9.2, v1.9.3, and v1.9.4 for PCI Express - Release Notes and Known Issues for ISE 10.1 IP Update 3 (IP_10.1.3)
This Release Notes and Known Issues Answer Record is for the Endpoint Block Plus Wrapper v1.9, released in ISE 10.1 IP Update 3, and contains the following information:
- General Information - New Features - Bug Fixes - Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf
The LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license.
Important Note: The Expansion ROM BAR is always enabled in the integrated block. The v1.6.1, v1.7.1, and v1.8 Endpoint Block Plus Core had a work-around that disabled the Expansion ROM BAR, since most applications do not make use of it. However, this work-around caused data corruption on incoming packets; see (Xilinx Answer 31164). The best solution to this problem was to remove the work-around causing the Expansion ROM to once again be enabled. You should review Chapter 3 (page 43) of the LogiCORE IP Endpoint Block Plus v1.9 for PCI User Guide (UG341): http://www.xilinx.com/support/documentation/ip_documentation/pcie_blk_plus_ug341.pdf
- ISE 10.1 SP3 software support - Added support for Virtex-5 FPGA TX150T and TX240T - Added support for ISE Project Navigator Flow - Added support for Expansion ROM BAR
CR 473951- Enabled Expansion ROM BAR Removed workaround to disable Expansion ROM BAR, as this was causing data corruption with certain traffic patterns. This feature is now permanently enabled and cannot be disabled. Users will need to respond to accesses to this BAR. Please refer to the Endpoint Block Plus v1.9 for PCI Express User Guide, Chapter 3, section on Base Address Registers for further details.
CR 476758 - TX lockup due to SRL 16E power on initialization issue Issue resolved where the Transmit path of the core locks up due to a Power On Initialization Issue with the SRL 16E Calendar logic.
CR 471589 - Update GTX wrapper Update the GTX wrapper to remove TXBUFFERBYPASS mode.
CR 476757 - TX lockup due to link partner advertising infinite data credits Issue resolved where a link partner advertising infinite data credits caused the transmit path of the core to lock up.
CR 472508 - Unexpected deassertion of trn_tdst_rdy_n in response to trn_tsrc_rdy_n deassertion Issue resolved where deassertion of trn_tsrc_rdy_n causes trn_tdst_rdy_n deassertion.
CR 472342 - Set Slot Clock bit in Link Status Register set incorrectly Selecting the Slot Clock Configuration option in the GUI does not set the Set Slot Clock bit in the Link Status Register.
CR 474746 - GUI Issue with Bar 3 configuration Issue resolved with GUI for Bar 3 configuration. When Bar 3 was selected for customization, the fields were not enabled for customization.
CR 437528 - GUI allowing 32-bit BAR to be set as Pre-fetchable Issue resolved where the GUI was allowing a BAR set as 32-bit BAR to also be set as Pre-fetchable.
CR 473935- System Verilog compatibility Updated user application (pci_exp_usrapp_com.v) to be System Verilog compatible.
CR 472801 - False failure reporting in PIO tests resolved PIO tests fixed to resolve false failure reporting. These tests were passing; however, a failure was reported.
CR 474892 - Data Corruption in example design test for 4-lane endpoint on FX70T Data corruption issue resolved in example design test for a 4-lane endpoint on FX70T.
CR 476165 - Extra feedback BUFG removed from PLL clocking network Removed extra feedback BUFG from the PLL clocking network. This BUFG is redundant because the user clock in the core does not need to be edge-aligned to the reference clock input.
CR 438737 - License Check Failure Warning issued while generating a core from CORE Generator Issue resolved where a Warning was being issued while generating the core from CORE Generator for a License Check failure.
There are three main components to the Endpoint Block Plus Wrapper for PCI Express:
- Virtex-5 FPGA Integrated Block for PCI Express - Virtex-5 FPGA GTP/GTX Transceivers - Block Plus Wrapper FPGA fabric logic