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AR# 31637

10.1 ISE - Synthesizing a design with an XMP submodule in Synplify Pro results in "Error: Reference to undefined module "system""


When I synthesize a design that includes an XMP submodule instantiated in the top level VHDL or Verilog source file, an error occurs in Synplify Pro 9.2.

The MicroBlaze portion of the design synthesizes fine in XST, but the remainder of the design produces an error when synthesized in Synplify Pro:

"Error: reference to undefined module "system""


To work around this error, remove the XMP file from the project and add it back into the project.

This problem has been fixed in the latest 10.1 Service Pack available at:

The first service pack containing the fix is 10.1 Service Pack 3.
AR# 31637
日期 07/26/2010
状态 Archive
Type 综合文章