AR# 31647


Endpoint Block Plus Wrapper v1.12 for PCI Express - Dual core implement_dual.bat file missing


Known Issue: v1.12 v1.11, v1.10.1, v1.10, v1.9.4, v1.9.3,v1.9.2, v1.9.1 and v1.9, v1.8, v1.7.1 


When I select the FX70TFF1136 device, CORE Generator produces a dual core example design. It correctly outputs an "" file, but not an "implement_dual.bat" file. Below are the contents of the "implement_dual.bat" file.


rem Clean up the results directory 

rmdir /S /Q results 

mkdir results 


echo 'Synthesizing HDL example design with XST'; 

xst -ifn xst_dual.scr 

move xilinx_dual_pci_exp_ep.ngc ./results/endpoint_blk_plus_v1_8_top.ngc 


cd results 


echo 'Running ngdbuild' 

ngdbuild -verbose -uc ..\..\example_design\xilinx_dual_pci_exp_blk_plus_8_lane_ep_xc5vfx70t-ff1136-1.ucf endpoint_blk_plus_v1_8_top.ngc -sd ..\..\..\ 


echo 'Running map' 

map -timing -ol high -xe c -pr b -o mapped.ncd endpoint_blk_plus_v1_8_top.ngd mapped.pcf 


echo 'Running par' 

par -ol high -xe c -w mapped.ncd routed.ncd mapped.pcf 


echo 'Running trce' 

trce -u -v 100 routed.ncd mapped.pcf 


echo 'Running design through netgen' 

netgen -sim -ofmt verilog -ne -w -tm xilinx_dual_pci_exp_ep -sdf_path ..\..\implement\results routed.ncd 


echo 'Running design through bitgen' 

bitgen -w routed.ncd 



Revision History 

09/16/2009- Updated for ISE 11.3 and core version v1.12. 

06/24/2009 - Updated for ISE 11.2 and core version v1.11. 

04/13/2009- Updated for ISE 11.1 and core version v1.10. 

09/12/2008 - Initial Release.
AR# 31647
日期 08/26/2013
状态 Active
Type 综合文章
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