AR# 32012


11.x ISE - Project Navigator does not honor "translate_off" and "translate_on" when building design hierarchy


A project source file might contain Synopsys constructs "translate_off" and "translate_on" for HDL constructs intended for simulation, but not synthesis.

Project Navigator seems to be building the hierarchy as though the "translate_off" and "translate_on" constructs are not present.


In ISE 10.1.03, Synopsys constructs "translate_off" and "translate_on", constructs are parsed by Project Navigator to determine hierarchy for VHDL source types. However, the Project Navigator Verilog parser does not yet support these constructs.

XST and other synthesis tools, available through Project Navigator, will correctly honor a Synopsys "translate_off" and Synopsys "translate_on" construct and omit design units from consideration.

This issue is resolved in the ISE Design Suite 12.1 release.
AR# 32012
日期 02/25/2011
状态 Archive
Type 已知问题
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