When customizing a Block Memory Generator v2.8 core in CORE Generator with ECC enabled, the "Total Port A Read Latency" displayed is incorrect.
Currently, when ECC is enabled, an additional clock cycle of latency is shown in the GUI. The core does not behave this way in hardware. For example, in hardware, if the core is configured for 2 clock cycles latency (with one of the available registering options) and ECC is enabled, the same latency should be seen in simulation. There is no difference in latency between ECC and non-ECC cores.
This is a known issue and will be resolved in the ISE 11.1 release of the core.