UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32037

LogiCORE Block Memory Generator v2.8 - Coregen GUI displays the incorrect latency for an ECC enabled core

描述

Keywords: LogiCORE, CORE, ip, Generator, Block, Memory, generator, bmg, blk, mem, core, blkmem, v2.7, v2.8, ECC, ecc, latency, read, GUI

When customizing a Block Memory Generator v2.8 core in CORE Generator with ECC enabled, the "Total Port A Read Latency" displayed is incorrect.

解决方案

Currently, when ECC is enabled, an additional clock cycle of latency is shown in the GUI. The core does not behave this way in hardware. For example, in hardware, if the core is configured for 2 clock cycles latency (with one of the available registering options) and ECC is enabled, the same latency should be seen in simulation. There is no difference in latency between ECC and non-ECC cores.

This is a known issue and will be resolved in the ISE 11.1 release of the core.
AR# 32037
日期 01/13/2009
状态 Active
Type 综合文章
的页面