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AR# 32055

10.1 EDK - xps_timer address width and data width are incorrect

Description

In the file "xps_timer.vhd", lines 361 and 362, the signal assignments appear to be incorrect: 

 

C_PLB_DWIDTH => C_SPLB_AWIDTH, 

C_PLB_AWIDTH => C_SPLB_DWIDTH, 

 

should be: 

 

C_PLB_DWIDTH => C_SPLB_DWIDTH, 

C_PLB_AWIDTH => C_SPLB_AWIDTH,

解决方案

The signal assignments are incorrect and should be changed as shown above. 

 

This problem is scheduled to be fixed in the 11.1 EDK toolset.

AR# 32055
创建日期 01/28/2009
Last Updated 05/23/2014
状态 Archive
Type 综合文章