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AR# 32061

LogiCORE Viterbi Decoder V6.2 - Is the synchronous reset input SCLR dependent upon clock enable CE?

Description

Is the synchronous reset input SCLR dependent upon clock enable CE?

解决方案

The synchronous reset (SCLR) works correctly only if the clock enable (CE) signal, if selected, is asserted High.  

 

Please see (Xilinx Answer 29448) for a detailed list of LogiCORE Viterbi Decoder Release Notes and Known Issues.

AR# 32061
创建日期 01/21/2009
Last Updated 05/23/2014
状态 Archive
Type 综合文章