In a x4 or x8 core simulation using the Downstream Port (DSPORT) model, a completion with length of 64 bytes or greater (in the Byte Count field) returned to the DSPORT does not come through to the TRN_RD port of the DSPORT.
This is a known issue with the Downstream Port simulation model. The issue does not affect the functionality of the Endpoint core itself.
To work around the issue, a modification to the DSPORT simulation model is required. The simulation model file requiring changes is named "pci_exp_4_lane_64b_dsport.v" for Verilog simulations, or "pci_exp_4_lane_64b_dsport.vhd" for VHDL simulations.
For Verilog, change the code beginning on line 155205 as follows (note the original line is commented below):