AR# 32108


11.1 Release Note - Timing Analyzer/TRCE - I see Component Switching Limit errors on a constraint that has zero items analyzed


Why do I see Component Switching errors when there are zero paths analyzed?


Timing constraint: TS_MY_CLK = PERIOD TIMEGRP "TNM_MY_CLK" 5 ns HIGH

50% INPUT_JITTER 0.1 ns;

0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints

5 timing errors detected. (0 setup errors, 0 hold errors, 5 component switching limit errors)



Some constraints will propagate through DCMs, PLLs, and other clock modifying blocks to create new, modified and related constraints. These constraints will effectively constrain or cover all of the paths that the source constraint was intended to cover. Therefore, the source constraint will show that there are zero items analyzed.

The source constraints are the only constraints that are being applied to IBUFG components and other source components up-stream in the clock path. This means that Component Switching Limit errors could still occur on a BUFGMUX that a source constraint would have to report on, even if that source constraint does not have any paths that are directly constrained.

AR# 32108
日期 12/15/2012
状态 Active
Type 综合文章
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