UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 32109

12.2 Timing Analysis/trce - I see Component Switching Limit errors on an input PERIOD constraint, but I am within specifications of the inputs

Description


When analyzing my Period constraint, I receive a Component Switching Limit errors on a PERIOD constraint. I should be within specifications.

Why do I see these errors?

解决方案

The Component Switching Limits can be different than the limits defined in the Datasheet, when a TEMPERATURE and/or VOLTAGE constraint is applied to the design. We have seen situations where changing the VOLTAGE constraint in the UCF will change the Component Switching Limit MAX/MIN frequencies.

The VOLTAGE and TEMPERATURE constraints are not supposed to change Component Switching Limits. This is a bug and is to be fixed in the next major release of the tools.

Make sure that you understand the component switching limit that you are seeing. The analysis below shows a violation on a source constraint for a given component. To identify where the violation is occurring, look at the "Location pin: DCM_ADV_X0Y1.CLKIN". In the following example the problem is associated with the DCM_ADV, not an IBUFG or any other components in the clock path:

================================================================================
Timing constraint: NET "Clk" PERIOD = 1 ns HIGH 50%;
0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
7 timing errors detected. (7 component switching limit errors)
Minimum period is 6.666ns.
--------------------------------------------------------------------------------
Component Switching Limit Checks: NET "Clk" PERIOD = 1 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: -5.666ns (period - min period limit)
Period: 1.000ns
Min period limit: 6.666ns (150.015MHz) (Tdcmpc)
Physical resource: dll0/CLKIN
Logical resource: dll0/CLKIN
Location pin: DCM_ADV_X0Y1.CLKIN
Clock network: Clk
--------------------------------------------------------------------------------
Slack: -5.666ns (period - min period limit)
Period: 1.000ns
Min period limit: 6.666ns (150.015MHz) (Tdcmpco)
Physical resource: dll0/CLK0
Logical resource: dll0/CLK0
Location pin: DCM_ADV_X0Y1.CLK0
Clock network: Clk0A
--------------------------------------------------------------------------------
Slack: -5.666ns (period - min period limit)
Period: 1.000ns
Min period limit: 6.666ns (150.015MHz) (Tdcmpc)
Physical resource: dll1/CLKIN
Logical resource: dll1/CLKIN
Location pin: DCM_ADV_X0Y0.CLKIN
Clock network: Clk
--------------------------------------------------------------------------------

AR# 32109
创建日期 04/07/2009
Last Updated 08/26/2010
状态 Active
Type 已知问题
Tools
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • More
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • Less