AR# 32132

描述

This answer record contains the Release Notes and Known Issues list for the CORE Generator tool LogiCORE IP Color Correction Matrix Core.

The following information is listed for each version of the core:

• New Features
• Bug Fixes
• Known Issues

解决方案

• (Xilinx Answer 34828) How do I simulate my Video IP pCore in EDK?

• Initial release in ISE 14.3 and Vivado 2012.3 tools

• All 7 series
• All Virtex-6
• All Spartan-6

• All 7 series

• ISE 14.3tool support
• Fixed clock domain issues with registers in the AXI4-Lite connection
• Increase of Coefficient range from [-4:4] to [-8:8]

• (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

• (Xilinx Answer 52215) Why does my core fail timing with an Critical Warning?

• Initial release in ISE 14.2 and Vivado 2012.2 tools

• All 7 series
• All Virtex-6
• All Spartan-6

• All 7 series

• ISE 14.2 tool support
• Added independent clock for AXI4-Lite

• N/A

• (Xilinx Answer 51589) Why does the Video IP stop working (i.e. producing TLAST output) when the optional AXI4-Lite interface is not selected in EDK?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
• (Xilinx Answer 51483) Why does my Video IP lock up when a partial input frame is passed by the Video In to AXI-4 Stream input core?

• Initial release in ISE 14.1 and Vivado 2012.1 tools

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000
• Virtex-6
• Spartan-6

• Virtex-7
• Kintex-7
• Artix-7
• Zynq-7000

• ISE 14.1tool support
• Virtex-7, Kintex-7, Artix-7 and Zynq device support
• AXI4-Stream interface support for the input and output interfaces
• AXI4-Lite bus interface support for the processor interface
• 16-bit data support

• N/A

• N/A

• Initial release in ISE Design Suite 13.3

• Virtex-7
• Virtex-7 XT (7vx485t)
• Virtex-7 -2L
• Kintex-7
• Kintex-7 -2L
• Virtex-6 XC CXT/LXT/SXT/HXT
• Virtex-6 XQ LXT/SXT
• Virtex-6 -1L XC LXT/SXT
• Virtex-6 -1L XQ LXT/SXT
• Spartan-6 XC LX/LXT
• Spartan-6 XA LX/LXT
• Spartan-6 XQ LX/LXT
• Spartan-6 -1L XC LX
• Spartan-6 -1L XQ LX

• ISE 13.3 tool support
• Virtex-7 and Kintex-7 device support
• AXI4-Lite bus interface support for the EDK Pcore interface

• CR 621035: The core will scale the data appropriately when the Input Bit Width is not equal to the Output Bit Width
• CR 570860: Software Enable is gated by vblank_in

• (Xilinx Answer 47048) - Why does the Color Correction Matrix pCore stop working after an an extended period of time?

• Initial release in ISE Design Suite 12.2

• Number of total columns and rows size increased to 4k x 4k pixels.
• Support for Spartan-6 and Virtex-6 devices added.
• Linux 32 and 64-bit support
• Pcore support for the XSVI bus added.

• (Xilinx Answer 35130) - Why do I get the following error when generating with a Design Linking License? "ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core."
• (Xilinx Answer 35433) - Why are all of my Color Correction Matrix elements converted to integers if I have set only one of them to an integer?

• (Xilinx Answer 33872) - "ERROR:sim - An IP generation script exited abnormally. Error found during generation."
• (Xilinx Answer 37987) - Where can I find UG762: Xilinx Streaming Video Interface User Guide?
• (Xilinx Answer 47048)- Why does the Color Correction Matrix pCore stop working after an an extended period of time?

• Initial release in ISE Design Suite 11.1

• Programmable matrix coefficients
• Selectable processor interface
  • EDK pCore
  • General Processor
  • Constant
• CMY input to RGB output color conversion
• Configurable 8, 10, and 12-bit input and output
• Independent clipping and clamping control
• Delay match support for up to 3 sync signals
• Efficient use of the XtremeDSP Slice
• ISE 11.1 design tools support

• N/A

• (Xilinx Answer 32340) - Why does my Image Pipe Video IP cores fail to update the netlist when the parameters or the license are changed, but the component name remains constant?
• (Xilinx Answer 33581) - Why is the output simulation netlist for my design encrypted, and only readable by ISE Simulator?
• (Xilinx Answer 33872) - "ERROR:sim - An IP generation script exited abnormally. Error found during generation."
• (Xilinx Answer 35130) - Why do I get the following error when generating with a Design Linking License? "ERROR:sim - Error: Netgen failed for v_cfa_v1_0.vhd. ERROR:NetListWriters:380 - The design contains secured core."
• (Xilinx Answer 35433) - Why are all of my Color Correction Matrix elements converted to integers if I have set only one of them to an integer?

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