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AR# 32146

10.1i EDK Sp3 - Known Issues for xps_deltasigma_dac_v1_00_a, software access via GPIO


EDK 10.1, 9.2, Sigma, Delta, XPS Delta-Sigma DAC (v1.00a), dsdac_v1_00_a, dsdac_v1_01_a, dsdac_v1_11_a, xps_deltasigma_dac_v1_00_a,

Software example provided with the Sigma Delta DAC does not work?

Why does the Sigma Delta DAC data output get corrupted?

How to generate Read_en signal for one clock cycle for Sigma Delta DAC?

Do we have any workaround for this issue?

With the provided Sigma Delta DAC software examples, especially with the xdsdac_intr_gpio_example.c , the output data gets corrupted because of the way the Read enable (Read_En) signal is generated from the software example. The minimum requirements for DAC data to work as Read_En signal should stay HIGH for one Clock cycle. So, it is not possible with the Software to assert the Read_En signal, exactly one clock cycle. For workaround, please refer to the following resolution.


Three software examples (i.e. two interrupt based and one non interrupt based) are provided in the EDK software Driver directory, which is named $:\Xilinx\10.1\EDK\sw\XilinxProcessorIPLib\drivers\dsdac_v1_11_a\examples

1. xdsdac_l0_example.c & xdsdac_l1_intr_example.c : This example does not use GPIO, but there are comments where the Read enable (Read_En) signal code should be inserted by the user:


* At this stage the Read_En signal should be driven high for a

* duration of OPB clk so that the data in Data FIFO will get converted.


2. xdsdac_intr_gpio_example.c: In this example, a GPIO is used for generating the Read_en signal. As you know, the minimum requirement for the READ_EN signal should stay HIGH for One Clock cycle, and this is not possible by software generation. Because of the irregular GPIO width, the Read_En for the DAC data will be corrupted.

Workaround for this issue:

Solution 1:

To get the provided examples working, the Read_En signal should be active for exactly one clock cycle with the help of two extra Flip-Flops. The First Flip-Flop GPIO will be given as a Clock input and the input data tied to HIGH. The second Flip-Flop uses the First Flip-Flop's output data (Q) as a data input, and the clock will be used a system clock. So, the output of the second Flip-Flop will be given as a READ_EN signal to the Sigma Delta DAC.

Attachments :

1. Block diagram for Flip-Flop addition for the READ_EN signal

2. EDK project for the Sparta-3ADSP for demo purpose.

AR# 32146
日期 12/15/2012
状态 Active
Type 综合文章