(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be (Xilinx Answer 22722) FIFO Generator Core now includes a User Guide in addition to a data sheet. Where can I find the User Guide for the FIFO Generator? (Xilinx Answer 24712) How do I test user logic that triggers ECC SBITERR and DBITERR outputs in FIFO Generator? (Xilinx Answer 30029) Setup/Hold time violations occur in the Unconstrained Path Report (Xilinx Answer 31144) Differences between FIFO v4.x (and newer) cores and v3.x (and prior) cores
New Features in v5.1
- ISE 11.1 support - Option to select WR_RST/RD_RST for independent clock block RAM or distributed RAM FIFOs - ECC error injection support for Virtex-6 block RAM and built-in FIFOs - Enhanced the core to block write/read operation when reset is asserted
Bug Fixes in v5.1
(Xilinx Answer 32032) Why is FWFT not available for Distributed RAM configurations? - Version fixed: v5.1 - CR 498565
- In the FIFO generator core, synchronous reset option is not available for Shift Register configuration - Version fixed: v5.1 - CR 448037
- In the FIFO generator VHDL behavioral model, array lengths do not match while loading the design for simulation - Version fixed: v5.1 - CR 476442 and 472517
- In the FIFO generator user guide, write order in figure 4-17 and 4-18 are not correct - Version fixed: v5.1 - CR 437899
- In the FIFO generator GUI, FIFO Read Depth reported incorrectly in GUI for FWFT w/Asymmetric Ports - Version fixed: v5.1 - CR 456488
- In the FIFO generator GUI, summary page does not explain MULT/BRAM routing contention for Spartan-3 devices - Version fixed: v5.1 - CR 480033
Known Issues in v5.1
(Xilinx Answer 24003) NC-Sim warning occurs when targeting Virtex-5 (Xilinx Answer 23691) Behavioral simulation models are not supported for built-in FIFO configuration (Xilinx Answer 20291) During simulation X_FF RECOVERY and SETUP warnings occur (Xilinx Answer 20271) Simulation error occurs on RESET (Xilinx Answer 30226) When writing to an EMPTY FIFO, PROG_FULL might assert earlier than expected (Xilinx Answer 31379) When importing an XCO file, user cannot change read/write clock frequencies with Built-in FIFO (Xilinx Answer 31381) Empty flag does not assert in Common Clock (block RAM based) behavioral model simulation