This Answer Record contains the Release Notes for the LogiCORE Tri-Mode Ethernet MAC v4.1 Core, which was released in the ISE 11.1 and includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
- ISE 11.1 software support
- Virtex-6 support
- Spartan-6 support
- Virtex-5 TXT support
- Option to generate without Half Duplex logic for Full Duplex applications
- Option to generate with a Media Independent Interface (MII) for 10Mb/s and 100Mb/s only Ethernet speed support
- Option to generate for 1Gb/s only Ethernet speed support: this option replaces the 1-Gigabit Ethernet MAC LogiCORE.
- Example Design Verilog language updated to Verilog 2001 syntax, including port map definitions, use of generate statements and generic/attribute set syntax.
- Example Designs for the Virtex-4 family have been updated with new logic for the GMII and RGMII physical interfaces to improve input setup/hold timing margins. The new logic now uses DCMs.
- RGMII Example Design (using clock enables) updated to allow transmitter global clock sharing across multiple core instantiations.
(Xilinx Answer 30644) When using RGMII and Spartan-3 family devices, the example design has a missing period contraint.
(Xilinx Answer 32629) LogiCORE Tri-Mode Ethernet MAC Core - Throughput in half-duplex GMII and RGMII modes