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AR# 32227

11.1 EDK, xps_ll_temac_v2_00_a - Tactical Patch to simulate Virtex-4 hard TEMAC block

Description

When the hard TEMAC block in Virtex-4 FX devices is simulated, the simulation model wrapper adds an additional delay, which causes loss of data going through the TEMAC.

Because of the delay, the frame going out had one byte dropped from the beginning, which caused the second byte of the destination address to become the first and the first byte of source address to become the last byte of the destination address. This caused an address miss-match on receive. It also caused the type/length field to be illegal. Both of these caused the hard TEMAC to drop the Frame on receive.

解决方案

In the past, the Virtex-4 hard TEMAC simulation model required a work-around in the VHDL of the TEMAC wrappers to delay a clock that comes out of the TEMAC, goes through a BUFG, and goes back into the TEMAC.

This work-around is no longer required in the latest simulation model, and therefore has to be removed.

The tactical patch has files that were modified near the top with the following change:

From

subtype delay is TIME;

Constant value1: delay := 1 ns;

To

subtype delay is TIME;

--Constant value1: delay := 1 ns;

Constant value1: delay := 0 ns;

The tactical patch can be downloaded from:

http://www.xilinx.com/txpatches/pub/applications/misc/ar32227.zip

1. Copy the xps_ll_temac_v2_00_a Core from the install folder "$XILINX_EDK\hw\XilinxProcessorIPLib\pcores\" to the pcores directory in your project, <Project>\pcores.

2. Extract the patch to "pcores\xps_ll_temac_v2_00_a\" folder and overwrite the existing files.

3. Regenerate the simulation HDL files.

This issue will be fixed in EDK 11.2i, which is scheduled to be released in mid-2009.

AR# 32227
创建日期 03/23/2009
Last Updated 12/15/2012
状态 Active
Type 综合文章