When using the recommended method for generating USRCLK and USRCLK2 to the Virtex-5 GTP via a DCM, the following error can occur in simulation:
Input Error : RST on instance EXAMPLE_TB.aurora_example_2_i.clock_module_i.clock_divider_i.genblk1 must be asserted for 3 CLKIN clock cycles.
In simulation, the TXOUTCLK port of the MGT will only start toggling 1 or 2 cycles prior to PLLLKDET asserting.
If PLLLKDET is used to drive the RST port of the DCM, this can lead to the above warning. In most cases this warning can be ignored, but in rare cases the DCM output will remain flat lined.
To work around this possibility, add a 3-cycle pipeline to PLLLKDET. This will add enough delay to correctly reset the DCM.
In hardware, this is not a problem as TXOUTCLK will be toggling at the correct speed for a large number of cycles prior to PLLLKDET asserting.