This Answer Record contains the Release Notes for the Aurora 8B/10B for Virtex-4 FX FPGAs v3.1 Core, released in ISE 11.1, and includes the following:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
The LogiCORE Aurora 8B/10B for Virtex-4 FPGAs requires a license to generate and implement the core. There is no charge for this license.
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- ISE 11.1 software support
- Insufficient simulation time (CR 479527).
- Timing violation at 6.25 Gb/s for 2-byte configuration (CR 479528).
The maximum line rate for 2-byte interface is restricted to 5 Gb/s since the maximum fabric frequency supported in Virtex-4 FX devices is 250 MHz.
Oversampling support has been removed.
- The valid line rates have changed with the removal of oversampling support. This change was due to low demand in order to reduce test burden, not due to a known issue with oversampling in previous cores.
Timing failure is observed at line rate above 4 Gb/s when transceivers are selected across columns.
- The issue is due to cross-column selection of transceivers. It is recommended to select transceivers in a single column.
Simplex timer option is tested only for line rate of 3.125 Gb/s.
- The Simplex timer value is set only for line rate of 3.125 Gb/s. To use simplex timer for other line rates, you should modify the timer value accordingly.
(Xilinx Answer 22845) - Design does not work in simulation at certain line rates. RXNOTINTABLE and RXRUNDISPERR observed at these line rates. This is a problem in GT11 swift model and simulator resolution. To work around the problem, select the reference clock frequency which results in integer VCO time period value in picoseconds.
(Xilinx Answer 24656) - Incorrect settings for RXVCODAC_INIT, VCODAC_INIT, TXCPSEL, RXCPSEL, and RXRCPADJ
4/24/09 - Initial Release
6/30/09 - Added note about oversampling support
8/6/09 - Added AR 24656, corrected Description section