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AR# 32235

Aurora 8B10B v4.1 - Release Notes and Known Issues for ISE 11.1

Description

Keywords: UG353, known restrictions

This Answer Record contains the Release Notes for the Aurora 8B10B v4.1 Core, released in ISE 11.1 IP Update 1, and includes the following:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

解决方案

General Information

The LogiCORE Aurora 8b10b requires a license to generate and implement the core. There is no charge for this license.

To generate the license, visit the product page at:
http://www.xilinx.com/products/ipcenter/aurora8b10b.htm


New Features

- Improved directory structure
- Multiple REF_CLK support for lanes more than 14
- Virtex-5 TXT device support


Bug Fixes

- Data outputs are X when RX_SRC_RDY_N is high in simplex designs (CR 471897)
- Incorrect values set for attribute DLL_FREQUENCY_MODE (CR 473336)
- Core generation fails when all the lane assignments are not done (CR 481515)
- Wrong REFCLK values available in the GUI (CR 493196)
- Description in user guide does not match behavior of RX_SOF_N signal (CR 499000)
- ISE flow given in user guide is not correct (CR 479688)
- Synthesis fails due to illegal place holder for a decimal number in UFC filter module (CR 468200)
- Flow control default option (none) not correctly picked up (CR 477439)
- CLKIN_PERIOD attribute of DCM set to incorrect values (CR 492852)
- Channel Bonding failure in streaming 9 lanes design (CR 469729)
- Core with lanes greater than 14 causes error because CHAN_BOND_LEVEL > 7 (CR 474630)


Known Issues

- Oversampling support for both GTP and GTX devices has been removed
- Currently, the cores support up to 16 lanes; if more than 16-lane support is required, contact auroramkt@xilinx.com
- Timing errors for designs with transceivers selected at extreme end of columns - refer to LogiCORE IP Aurora 8B10B v4.1 User Guide (UG353) for more details
- Manual edits required to use "orphaned" transceivers when Aurora uses only 1 transceiver in a DUAL (CR 503600) - refer to LogiCORE IP Aurora 8B10B v4.1 User Guide (UG353) for more details
- SCP and ECP do not support back to back frames (CR 505495) - The Aurora core requires that the SCP is transmitted in the most significant lane and that ECP is transmitted in the least significant lane. This reduces the bandwidth if the frames do not fit this scheme.
- (Xilinx Answer 32218) Aurora does not initialize properly due to unstable clock during power-up
- (Xilinx Answer 32694) Errors in synthesis for cores targeting the Virtex-5 TXT's right-hand GTX column
- (Xilinx Answer 32695) Cannot directly replace Aurora transceiver tile wrapper with GTX Wizard's transceiver tile wrapper


Revision History
4/24/09 - Initial Release
5/12/09 - Added references to Answer Records 32694, 32695 and reorganized known issues section
5/22/09 - Corrected AR description
AR# 32235
创建日期 04/22/2009
Last Updated 05/22/2009
状态 Active
Type 综合文章