The Endpoint Block Plus Wrapper for PCI Express is affected by the problem outlined in (Xilinx Answer 32164).
解决方案
Xilinx has added the fix outlined in (Xilinx Answer 32164) to the Block Plus Core. This fix is to be included in the v1.10.1 release that is scheduled to be available when 11.1 is released (planned for April 27, 2009).
Until then, users that are experiencing this problem can add the following constraints to the FXT UCF file:
This problem does not affect Virtex-5 FXT designs using synchronous clocking, or any Virtex-5 LXT (GTP RocketIO) design. These constraints should not be applied to LXT/SXT designs.
04/09/2009 - Updated work around to include clock correction sequence 4/03/2009 - Added work-around and release date information for fix. 03/13/2009 - Initial Release.