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  1. 赛灵思 - All Programmable
  2. 技术支持
  3. AR# 32270: Endpoint Block Plus Wrapper v1.9 for PCI Express - Using non-synchronous links with Virtex-5 FXT (GTX RocketIO) could result in data errors

AR# 32270

Endpoint Block Plus Wrapper v1.9 for PCI Express - Using non-synchronous links with Virtex-5 FXT (GTX RocketIO) could result in data errors

Description

Known Issue: 1.9, 1.8, 1.7.1, 1.7, 1.6.1, 1.6, 1.5.2, 1.5.1, 1.5, 1.4, 1.3, 1.2, 1.1

The Endpoint Block Plus Wrapper for PCI Express is affected by the problem outlined in (Xilinx Answer 32164).

解决方案

Xilinx has added the fix outlined in (Xilinx Answer 32164) to the Block Plus Core. This fix is to be included in the v1.10.1 release that is scheduled to be available when 11.1 is released (planned for April 27, 2009).

Until then, users that are experiencing this problem can add the following constraints to the FXT UCF file:

Lane 0/1:

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" CLK_COR_ADJ_LEN_0 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" CLK_COR_DET_LEN_0 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" CLK_COR_ADJ_LEN_1 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" CLK_COR_DET_LEN_1 = 2;

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" CLK_COR_SEQ_1_1_0 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" CLK_COR_SEQ_1_1_1 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" CLK_COR_SEQ_1_2_0 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" CLK_COR_SEQ_1_2_1 = 10'b0100011100 ;

Lane 2/3:

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" CLK_COR_ADJ_LEN_0 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" CLK_COR_DET_LEN_0 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" CLK_COR_ADJ_LEN_1 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" CLK_COR_DET_LEN_1 = 2;

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" CLK_COR_SEQ_1_1_0 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" CLK_COR_SEQ_1_1_1 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" CLK_COR_SEQ_1_2_0 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" CLK_COR_SEQ_1_2_1 = 10'b0100011100 ;

Lane 4/5:

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" CLK_COR_ADJ_LEN_0 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" CLK_COR_DET_LEN_0 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" CLK_COR_ADJ_LEN_1 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" CLK_COR_DET_LEN_1 = 2;

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" CLK_COR_SEQ_1_1_0 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" CLK_COR_SEQ_1_1_1 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" CLK_COR_SEQ_1_2_0 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[4].GT_i" CLK_COR_SEQ_1_2_1 = 10'b0100011100 ;

Lane 6/7:

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" CLK_COR_ADJ_LEN_0 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" CLK_COR_DET_LEN_0 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" CLK_COR_ADJ_LEN_1 = 2;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" CLK_COR_DET_LEN_1 = 2;

INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" CLK_COR_SEQ_1_1_0 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" CLK_COR_SEQ_1_1_1 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" CLK_COR_SEQ_1_2_0 = 10'b0100011100 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[6].GT_i" CLK_COR_SEQ_1_2_1 = 10'b0100011100 ;

This problem does not affect Virtex-5 FXT designs using synchronous clocking, or any Virtex-5 LXT (GTP RocketIO) design. These constraints should not be applied to LXT/SXT designs.

For information regarding clocking and PCI Express, see (Xilinx Answer 19760).

Revision History

04/09/2009 - Updated work around to include clock correction sequence
4/03/2009 - Added work-around and release date information for fix.
03/13/2009 - Initial Release.
AR# 32270
日期 08/09/2010
状态 Active
Type ??????
IP
  • Virtex-5 Integrated Endpoint Block
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