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AR# 32318

MIG v3.0, Virtex-5 QDRII - Design does not complete calibration in hardware when using Synplify Pro 9.6.2 as the synthesis tool

Description

There is a known issue when the MIG 3.0 Virtex-5 QDRII design is synthesized using Synplify Pro 9.6.2. This version of Synplify Pro fails to generate the negative edge of clk0. This clock is needed to clock the output address and command signals. Instead, the positive edge of clk0 is used to clock out the outputs, which causes these signals to fail setup time at the QDRII memory. As a result, the design is stuck in calibration.

解决方案

To work around this Synplify Pro issue, add a temporary signal called 'clk_temp' with a syn_keep attribute in the infrastructure.v module. The existing assignment for clk180 needs to be commented out and the value of clk_temp signal, then assigned to the clk180 (an output of the infrastructure.v) module.

Make the following code changes in the infrastructure.v module:

wire clk_temp /* synthesis syn_keep = 1 */;
assign clk_temp = !clk0;
assign clk180 = clk_temp;
//assign clk180 = ~clk0;

This issue is resolved in the latest version of Synplify Pro - C.03.2009.
AR# 32318
创建日期 03/24/2009
Last Updated 12/15/2012
状态 Active
Type 综合文章
器件
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
IP
  • MIG