AR# 32360

11.1 ISE Simulator (ISim) - Issues when using assert / report commands in VHDL

描述

I use the Assert / Report VHDL I/O functions in order to write messages to the simulator console. However, when I write messages using this syntax:

assert false report Message.all severity warning;

DEALLOCATE (Message);

the output shows up incomplete when running the simulation in batch mode.

For example:

Finished circuit initialization process.

(/testbench/config_test/).the design...

Running the same simulation via the ISim GUI results in the correct console output:

Finished circuit initialization process.

at 200 ns: Note: Resetting the design...

(/testbench/config_test/).

How can I resolve this issue?

解决方案

This is a known issue with ISim in ISE Design Suite 11.1 tools and it has been fixed in ISE Design Suite 11 Update 2 (11.2) . Please download and install the latest ISE Design Suite update from the Download Center at: http://www.xilinx.com/support/download/index.htm.

链接问答记录

相关答复记录

Answer Number 问答标题 问题版本 已解决问题的版本
33381 ISE Design Suite 11 - ISE Simulator (ISim) Known Issues N/A N/A
AR# 32360
日期 12/15/2012
状态 Active
Type 综合文章