When I run DRC in PlanAhead after creating my pin-out, I do not receive any errors. Should I use this as a guarantee that there are no conflicts in these constraints?
The PlanAhead DRCs are designed to catch conflicts as early in the flow as possible to expedite Pin Planning. However, the DRCs are not comprehensive. Place and Route should still be considered the sign-off tool for a pin-out.
If you encounter errors on I/O Placement in Place and Route that were not caught in PlanAhead, open a WebCase with Xilinx Technical Support so that the DRCs can be updated in a future release: