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AR# 32396

13.1 CORE Generator - Generating a core through Project Navigator causes VHDL example files to be overwritten

Description

If an IP core is created in or regenerated through Project Navigator, the functional model and other supporting HDL files are generated for both HDL languages. For IP cores which generate an example design, some of the file names are the same in the "simulation" folder regardless of the language generated, so files are overwritten and do not work if it is not for the first language generated.

This issueaffects MIG, Endpoint Block for PCI Express Core, Serial Rapid I/O, and some networking cores which generate an example design.

解决方案

Writing out source files for both Verilog and VHDLis expected behavior. However, for this set of IP cores, this behaviorinterferes with the simulation scripts for the example designs.

To work around this issue,open theCORE Generator tool outside of Project Navigator and regenerate the core with the preferred language selected in the project properties.

This issue has been resolved in ISE Design Suite 13.2.

链接问答记录

主要问答记录

Answer Number 问答标题 问题版本 已解决问题的版本
40493 13.x CORE Generator - Known Issues N/A N/A
AR# 32396
创建日期 04/09/2009
Last Updated 05/22/2012
状态 Archive
Type 已知问题
Tools
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • ISE Design Suite - 11.2
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  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE - 9.1i
  • ISE - 9.2i
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 13.1
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