You are using a deprecated Browser. Internet Explorer is no longer supported by Xilinx.
EDK 11.1, plbv46_pcie_v3_00_a - Data sheet contains incorrect information
The plbv46_pcie_v3_00_a Product Specification document contains the following discrepancies:
- x1, x4, and x8 lane support; this should be corrected to x1 lane support only.
- LinkUp output needs to be added to the I/O port list.
- Footnotes in resources table need to have 6-ipifbar, 3 pciebar, and x8 lane support changed to: 1-ipifbar, 1-pcibar, and x1 lane support.