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AR# 32420

11.1 ChipScope Pro tool - Known Issues


The ISE Design Suite 11.1 Release Notes packaged with your ISE software shipment, or found on the Electronic Fulfillment site, contain installation instructions, system requirements, and other general information about ISE software 11.1, including the ChipScope Pro tool.

This Known Issues Answer Record is a supplement to the 11.1 Release Notes and contains links to information on known issues in the ChipScope Pro debug and verification tool that might be resolved in service packs or future versions.


Known Issues

(Xilinx Answer 32422) 11.1 ChipScope Pro - Device Support Deprecated

(Xilinx Answer 32424) 11.1 ChipScope Pro Inserter - I cannot probe nets in my IP core

(Xilinx Answer 32426) 11.1 ChipScope Pro CORE Generator - NCF files are not created for my ChipScope core

(Xilinx Answer 31788) 11.1 ChipScope Pro - "ERROR:MapLib:990 - Map has detected that you are using ChipScope Pro cores generated prior to version 10.1"

(Xilinx Answer 32429) 11.1 ChipScope Pro - Analyzer now automatically detects the buses in my design

(Xilinx Answer 32430) 11.1 ChipScope Pro IBERT - Synthesis fails for Virtex-5 GTX design

(Xilinx Answer 32431) 11.1 ChipScope Pro IBERT - Generation fails at MAP for designs on Virtex-5 LX20T

(Xilinx Answer 32432) 11.1 ChipScope Pro Analyzer - Auto Bus Creation does not work for VIO

(Xilinx Answer 32433) 11.1 ChipScope Pro Analyzer - Auto Bus Creation creates 1 bit buses

(Xilinx Answer 32434) 11.1 ChipScope Pro Analyzer - Analyzer does not recognize Partial Bit files

(Xilinx Answer 32435) 11.1 ChipScope Pro Analyzer - System Monitor External channel name is not updated when new channel selected

(Xilinx Answer 32299) 11.1 ChipScope Pro - Inserter "WARNING:sim:356 - The parameter "Exclude_From_Data_Storage_1" is disabled, its value defaults from false to true"

(Xilinx Answer 32428) 11.1 ChipScope Pro CORE Generator - The Trigger Port numbers are confusing

(Xilinx Answer 32664) 11.1 ChipScope Pro - Analyzer - WARNING: Security:43 - No license file was found in the standard Xilinx license directory

Resolved in 11.1

(Xilinx Answer 32423) 10.1 ChipScope Pro - NCF file for VIO core is missing constraints

(Xilinx Answer 31857) 10.1 ChipScope Pro IBERT - Virtex-5 TXT MGT locations are reported incorrectly

(Xilinx Answer 32365) 10.1.03 ChipScope Pro Inserter - ATC2 core fails to generate when "Endpoint Type" is set to "Differential"

(Xilinx Answer 31746) 10.1 ChipScope Pro - When I generate my ATC2 Agilent using the Inserter flow, the pins are locked to incorrect locations

(Xilinx Answer 32425) 10.1 ChipScope Pro - "ERROR:Xst:1617 - Processing TIMESPEC TS_U_TO_D: user TIMEGRP 'D_CLK' must be previously defined in FROM/TO constraint"

(Xilinx Answer 32427) 10.1 ChipScope Pro - When using Inserter, Translate takes much longer with ChipScope cores inserted than it did in 9.2

(Xilinx Answer 32428) 10.1 ChipScope Pro Inserter - "ERROR:NgdBuild:924 - bidirect pad net '<net_name>' is driving non-buffer primitives"

(Xilinx Answer 30985) 10.1 ChipScope Pro Inserter - "WARNING:Par:288 - The signal <signal_name > has no load. PAR will not attempt to route this signal."

(Xilinx Answer 31697) 10.1.03 ChipScope Pro GTP SIOTK - Errors in the middle of eye during IBERT parameter sweep

(Xilinx Answer 32228) 10.1 ChipScope - ATC2 Error-[URMI] Instances with unresolved modules remain in the design

For all 11.2 and 11.3 known and resolved issues please see: (Xilinx Answer 32656)

AR# 32420
日期 03/11/2010
状态 Active
Type 已知问题