AR# 3243: M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.
AR# 3243
M1.4 Map - Timespec'ing RAMS (dualport) to FFS only covers SPO path.
Description
When using the TIMEGRP constraint in a UCF to constrain the paths between the dual port RAMs and connected flops, only the F LUTs get referenced in the PCF. This only covers the SPO (associated with the FLUT) but not the DPO (associated with G LUT).
Notice the first TIMEGRP line contains only BEL "ram16d_spo", repeated twice. The BEL's name "ram16d_spo" is based on the output SPO net. The DPO net has the name "ram16d_dpo", so the TIMEGRP line was changed like so:
This issued has been fixed in the mapper so that the correct .pcf constraints are written. This fix is included in the current M1.4 Core Applications patch available from the Xilinx Download Area: