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AR# 32471

11.1 PlanAhead - False IDLYCTRL0 Error on Virtex-5 floorplans


When I run DRC on my Virtex-5 design, an error occurs that states there is a IDELAYCTRL constrained to a bank with no IODELAYs. I have verified that there are IODELAYs used in that bank. Can I safely ignore this error?


This error can be safely ignored if there are IODELAYs used in Fixed or Variable mode in the bank.  


This issue is scheduled to be fixed in the 11.2 release of PlanAhead.

AR# 32471
日期 05/21/2014
状态 Archive
Type 综合文章