AR# 32500

LogiCORE Initiator/Target v4.8 for PCI - Implementing XC5vLX110t-FF1136 might cause PAR error: "ERROR:Route:472 - This design is unrouteable."

描述

Known Issue v4.8

When implementing a 66 MHz design for the XC5vLX110t-FF1136 in 11.1, it might give this error during PAR:

"ERROR:Route:472 - This design is unrouteable.

To evaluate the problem please use fpga_editor.

Routing Conflict 1: Net:M_CBE<7> on pin DX on location SLICE_X5Y95

Net:XPCI_WRAP/TRDYI_78_ML_BYPASS on pin B4 on location SLICE_X4Y96

Conflict detected on wire: PINBOUNCE(-121639,51016)"

解决方案

To resolve this issue, add the following constraints to the UCF file:

INST "XPCI_WRAP/XPCI_CORE/BU2/U0/pci64_inst/PCI_LC_I/MASTER/IRDY/

M_FIRSTIN2" XBLKNM = XLNX_WA1;

INST "XPCI_WRAP/XPCI_CORE/BU2/U0/pci64_inst/PCI_LC_I/MASTER/IRDY/

M_FIRST" XBLKNM = XLNX_WA1;

INST "XPCI_WRAP/XPCI_CORE/BU2/U0/pci64_inst/PCI_LC_I/MASTER/IRDY/

M_FIRSTIN1" XBLKNM = XLNX_WA1;

INST "XPCI_WRAP/XPCI_CORE/BU2/U0/pci64_inst/PCI_LC_I/MASTER/REQ64

/NS_REQ64_28" XBLKNM = XLNX_WA1;

INST "XPCI_WRAP/XPCI_CORE/BU2/U0/pci64_inst/PCI_LC_I/MASTER/REQ64

/NS_REQ64_52" XBLKNM = XLNX_WA1;

Revision History

04/13/2008 - Initial Release

AR# 32500
日期 12/15/2012
状态 Active
Type 综合文章