AR# 32503


SPI-3 PHY Layer v5.2 - Virtex-5 cores see PAR timing failures for polled cores


Some core configurations exhibit PAR timing failures for polled cores (tx_transfer_control = polled) in Virtex-5, in which the critical path is a block RAM output to a FF to a pad (output PTPA). The block RAM is placed on the left side of the chip, and the pad on the right side (the FF is embedded in the IOB).  


The specific timing failure would appear as follows: 


PAR error message: "WARNING:Par:62 - Your design did not meet timing." 


PAR failing constraint:  

* TS_tfclk_clk0 = PERIOD TIMEGRP "tfclk_clk | SETUP | -1.426ns| 12.466ns| 1| 1426 

0" TS_TFCLK PHASE 1.502 ns HIGH 50% | HOLD | 0.222ns| | 0| 0  


Trace report info: 

Timing constraint: TS_tfclk_clk0 = PERIOD TIMEGRP "tfclk_clk0" TS_TFCLK PHASE  

1.502 ns HIGH 50%; 


Slack: -1.426ns (requirement - (data path - clock path skew + uncertainty)) 

Source: spi3_phy_tx0/core/core_spi3_phy_tx/core_spi3_phy_tx_xst/U0/tx_flow0/polled_mode.large_ptpa.tx_flowram0/bram_table (RAM) 

Destination: spi3_phy_tx0/core/core_spi3_phy_tx/core_spi3_phy_tx_xst/U0/tx_flow0/polled_mode.large_ptpa.tx_flowram0/TPA (FF) 

Requirement: 4.808ns 

Location Delay type Delay(ns) Physical Resource 

Logical Resource(s) 

------------------------------------------------- ------------------- 

RAMB36_X2Y11.DOADOL0 Trcko_DOA 2.190 spi3_phy_tx0/core/core_spi3_phy_tx/core_spi3_phy_tx_xst/U0/tx_flow0/polled_mode.large_ptpa.tx_flowram0/bram_table 


OLOGIC_X2Y110.D1 net (fanout=1) 3.483 spi3_phy_tx0/core/core_spi3_phy_tx/core_spi3_phy_tx_xst/U0/tx_flow0/polled_mode.large_ptpa.tx_flowram0/bram_rd_data 

OLOGIC_X2Y110.CLK Todck 0.434 PTPA_OBUF 


------------------------------------------------- --------------------------- 


Total 6.107ns (2.624ns logic, 3.483ns route) 

(43.0% logic, 57.0% route)


This can be resolved by locking down the location of the block RAM and the output pin close to each other. 


Example UCF constraints: 


NET "PTPA" LOC = "AB7"; 

INST "*bram_table" LOC = RAMB36_X4Y11; 


Revision History 

04/27/2009 - Initial Release

AR# 32503
日期 05/23/2014
状态 Archive
Type 综合文章
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